Careers
Position: Senior VLSI Analog Design Engineer
Role Description:
Sr. VLSI Analog engineer to join our analog team at PLSense
The role includes a variety of analog and circuit chip design tasks, validation of the analog portion of the product as well as participation in designing PLSense's next generation product
Requirements:
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7+ years’ experience
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Knowledge in VLSI circuit and analog designs (op-amp, DC2DC, DAC, comparators, Oscillators, etc.)
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Knowledge in CMOS technologies 40nm and below. FinFET technologies experience is an advantage
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Knowledge in chip design spice simulations tools (Cadence, Synopsys)
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experience with Lab analog validation practices is an advantage
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Independent, team player
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Education: BSc in Electrical engineering, higher degree is an advantage
Position: VLSI Design Manager
Role Description:
Managing the VLSI design and verification teams of PLSense
Requirements:
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10+ years’ experience
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At least 5 year of VLSI management experience
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Knowledge of Verilog and different design technics
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Knowledge of different Verification methodologies such as UVM and System Verilog
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Knowledge of Static Timing Analysis is an advantage
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Knowledge of FPGA development is an advantage
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Knowledge at CPU architectures such as ARM, ARC and RISC-V is an advantage
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Good managing skill
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Team player and versatile manager
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Education: BSc in Electrical engineering, MSc is an advantage
Position: Senior Board Design Engineer
Role Description:
Design and implementation of different evaluation and reference design boards for the PLSense chips. Including customer support for PCB issues and requirement
Requirements:
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10+ years’ experience
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Good knowledge and experience with board design
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Knowledge of IoT systems and battery-operated board design requirements
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Experience in working and management of different contractors for PCB layout, manufacturing, and assembly
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Knowledge and experience with Lab work and board bring-up
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Analog block validation knowledge is an advantage
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Experience with Python or Perl scripting language
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Basic C programming
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Independent, team player
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Education: BSc in Electrical engineering, MSc is an advantage
Position: Senior CAD/SoC Engineer
Role Description:
Participate in developing and executing RTL2GDII Chip implementation
Build low-power UPF specification, analyze power in all phases of the design cycle
Develop an optimized low power Synthesis flow – including UPF - while meeting aggressive performance, area, and cost targets
Analyze post silicon chips for power and performance
Requirements:
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5+ years of experience
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Experience in Synthesis
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Experience in building UPF specification and flow
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Broad knowledge of STA and SDC
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Knowledge in RTT2GDSII tools and flows
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knowledge in programming, (for example: C, Python, tcl , perl, etc.)
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Basic Verilog knowledge
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Independent, team player
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Education: BSc is Electrical engineering, or Computer Science, MSc is an advantage
Position: Senior DFT Engineer
Role Description:
Lead the complete DFT development of PLSense chip design by preparing the DFT specifications, define the SoC test interface and develop and implement the DFT in the silicon
Generate structural test vectors, analyze and improve coverage
Requirements:
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5+ years of DFT experience, leading DFT efforts for complex chip designs
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Experience with developing DFT specifications and driving DFT architecture and methods for VLSI designs
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Knowledge of Verilog and / or VHDL, and experience with simulators and waveform debugging tools
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Experience at debug ATPG patterns, compressed ATPG patterns, MBIST, and JTAG related issues
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Experienced with STA constraints development and analysis for DFT modes and SDF simulations
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Basic C programming
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Independent, team player
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Education: BSc in Electrical engineering, MSc is an advantage
Position: Software Engineer
Role Description:
Embedded SW engineer with more than 2 years’ experience. The job includes writing applications, API and drivers for PLSense MCU chip
Requirements:
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Strong knowledge in C
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Independent worker and a good team player
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Education: BsC is computer engineering
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Experience: minimum 2 years in embedded SW programming
Preferred qualifications:
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Knowledge of RISC-V
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Experience with low-level SW and the interaction with HW devices
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Knowledge in low-level protocol such as SPI, I2C and UART
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Knowledge with RTOS such as FreeRTOS
Position: VLSI Design Engineer
Role Description:
Design and integration of different blocks and full chip. Running verification and coverage tests
The development will use Verilog code
Requirements:
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Minimum 2 years’ experience
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Knowledge at Verilog and different design technics
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Knowledge at UVM and System Verilog is an advantage
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Knowledge at CPU architecture like ARM, ARC and RISC-V is an advantage
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Experience at Python or Perl scripting language is an advantage
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Basic C programming
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Independent, team player
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Education: BsC is Electrical engineering, MsC is an advantage