Careers
Position: Software Engineer
Role Description:
Embedded SW engineer with more than 2 years’ experience. The job includes writing API and drivers for PLSense MCU chip.
Requirements:
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Independent worker and a good team player.
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Knowledge of RISC-V architecture is an advantage
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Education: BsC is computer engineering, MsC is an advantage.
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Experience: 2-5 years and more in embedded SW programming.
Position: Analog Design Engineer
Role Description:
Senior Analog engineer with more than 5 years’ experience. Experience in development of key circuit and analog components such as RAM/ROM, IO, ESD, DC2DC, ADC.
Requirements:
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Minimum 5 years’ experience.
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Independent, team player.
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Knowledge in complex circuit and analog design.
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Education: BsC is Electrical engineering, MsC is an advantage.
Position: VLSI Design Engineer
Role Description:
Design and integration of different blocks and full chip. Running verification and coverage tests.
The development will use Verilog code.
Requirements:
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Minimum 3 years’ experience.
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Knowledge at Verilog and different design technics.
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Knowledge at UVM and System Verilog is an advantage.
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Knowledge at CPU architecture like ARM, ARC and RISC-V is an advantage.
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Experience at Python or Perl scripting language.
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Basic C programming.
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Independent, team player.
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Education: BsC is Electrical engineering, MsC is an advantage.
Position: Verification Engineer
Role Description:
Development a verification environment for block level and full chip. Running verification and coverage tests.
The development will use both UVM and System Verilog code.
Requirements:
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Minimum 3 years’ experience.
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Knowledge at UVM and System Verilog
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Knowledge at CPU architecture like ARM, ARC and RISC-V is an advantage
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Experience at C programming
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Experience at Paython or Perl scripting language
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Independent, team player.
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Education: BsC is Electrical engineering, MsC is an advantage.
Position: CAD/SoC Engineer
Role Description:
Participate in developing and executing RTL2GDII Chip implementation.
Use best-in-class methodologies to optimize the design for low power while meeting aggressive performance, area and cost targets.
Develop and use metric-driven techniques to ensure first-pass working silicon.
The tool and flows include: Synthesis, DFT, STA, Power Intend and verification, P&R and more.
Analyze post silicon chips for power and performance.
Participate in selecting the next CMOS processes.
Requirements:
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Knowledge in RTL2GDSII tools and flows.
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knowledge in programming, (for example: C, Python, tcl , perl) .
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Basic Verilog knowledge.
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Independent, team player.
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Education: BsC is Electrical engineering, or Commuter Science, MsC is an advantage.